Tuesday 22 September 2020 |
Expertise in Front-end RTL design and SoC integration of multi-million gates IPs and SoCs for a variety of industry verticals like mobile, processors, networking and multimedia. Experience in the design verification involving standardized methodology like UVM based functional and formal techniques, VIP development, Equivalence checking and Gate level simulations of complex IP and SoC designs.
Our team of experienced design engineers, complemented by a group of mid-level engineers have worked on multiple aspects of the RTL design flow on chips used in the automotive, mobile, networking, multimedia and processor industries. The following schematic demonstrates how Hirexa’s expertise helps the pieces of the jigsaw fall into place.
Hirexa’s verification team has proven expertise on taking complete ownership of verification of a design from scratch – whether that is an IP/SOC/subsystem – and taking it to verification closure by performing the following activities:
Hirexa has a small but capable team with hands-on expertise in various aspects of the chip design flow where SystemC plays a critical role. They are represented in the chart below.
The AMS verification team at Hirexa has the skillsets required to execute on: