Tuesday 22 September 2020   |   


Alternate Text


PHYSICAL DESIGN, DFT, STA SIGNOFF AND PHYSICAL VERIFICATION


Expertise in place & route for block build/full chip development with timing closure using industry standard tools for tasks like Synthesis, Floor Plan, Placement, CTS, Signal Integrity, IR Draw, EM, Low Power Checks and Signoff checks. Extensive Knowledge in physical verification like DRC, LVS, Antenna, Density in latest nodes like 14nm, 10nm. Experience in DFT Techniques like Scan, Bist, ATPG, Boundary Scan.


IMPLEMENTATION ENGINEERING

At Hirexa Solutions, Physical Design Service offerings are comprised of having expertise in following domains



Hierarchical/Flat level chip implementation

  • IO Planning/Floor-Planning/Power Planning/P&R/Metal Fills
  • Expertise in 14nm, 28nm and above.
  • Flip Chip designs with Package Level Interactions and closure.
  • Design Partitioning and Hardening.
  • DFT scan insertion and Timing closure in Functional/Test modes.


Core Hardening or block Build development

  • Abstract view generation and pinning.
  • UPF/CPF flow development.
  • MMMC based timing optimization.
  • Timing Budgeting and closure.


Die Size optimization and related scripting and automation support

  • Area estimation of Macros/IOs
  • Estimation based on Bond Pads, available logic area.


Physical Verification/DFM support for Hard Macros and full chip level

  • DRC/LVS/Antenna/Density checks.


Signoff timing closure with X-talk effects, OCVs and ECO’s implementation

  • Experience in using NLDM/CCS timing models
  • Timing closure for Functional/Shift/Capture modes.
  • X-talk noise and delay effect on timing.


Low Power Implementation for Static/Dynamic reductions

  • Dynamic power reductions using clock gating/Retention logic/Switch cells
  • Redhawk tool expertise in IR Drop analysis.
  • Decap/TapCells/EndCap cells/Clamp cells insertion and optimization.


Synthesis/Formal equivalence/UPF flow/CLP checks support

  • Flat/Hierarchical synthesis approach.
  • Scan chain insertion for improving testability and test coverage.


Extensive support on DFT insertion and Simulations

  • Extensive support in Scan, BIST, JTAG, EDT, BSC logic Insertion
  • ATPG fault coverage analysis.
  • Deep support in Mentor/Synopsys tool sets.


EDA/CAD flow & methodology support

  • Back-End flow development and support
  • System administration with LSF/EOD/Licence management/tools installation support.

Our philosophy is to become a dedicated service partner to our esteemed clients in all the above niche skills requirements on multiple projects and earn the most trusted design service partner. Our engineers are agile and possess the quality of quickly adapt the new flows and methodology to deliver quality results.



Design Implementation

Alternate Text


Library and Flow Development

Alternate Text


IC Packaging Co Design

Alternate Text






Alternate Text